Block
Your SoC Verification Solution
Block
Your SoC Verification Solution

AutoDV is a TESDA Premier SoC Verification Solution providing a comprehensive set of advanced tools designed specifically for design and verification teams. With AutoDV, engineers can utilize its unified platform to take on tough SoC verification challenges without difficulty, offering automated solutions for SoC parsing, verifier integration, and verification platform creation.

AutoDV is meant to completely transform your verification process into a powerful tool. Imagine one single-experience platform that brings your whole team together, allowing you to share knowledge more efficiently and collaborate more effectively while seamlessly integrating your company’s internal methods. AutoDV does exactly that by transforming how you work.

Pulpino Attached with Verifier

AutoDV gives you access to features such as automatic SoC parsing, a drag-and-drop TESDA verifier, and instant generation of a verification platform. Just like in the picture, the user can attach the verifier to the SoC design, improving its verification process through the automated testbench, guaranteeing the availability of tests for every hierarchy of the SoC design. Say goodbye to the awful, long, and frustrating verification cycles. Rather than weeks or even months, with AutoDV, you can reduce your verification timeline to days.

Why AutoDV?

➛  Speed & Efficiency: AutoDV relies on automated processes, eliminating verification times and reducing your project timeline without compromising quality.

➛  Consistency & Accuracy: Our unified framework ensures no errors in every verification cycle, and we unify it through iterations to ensure consistency in each cycle.

➛  Scalability: AutoDV scales with you, whether you are performing SoC-level verification or need rapid platform generation across multiple design versions.

TESDA Focus on SoC Verification Technology

As illustrated in the graph, at IP/block level, the main concern is functional coverage. At the subsystem level, the main concern will be connection and configuration coverage. While at SoC level, we assume all IP/blocks and subsystems within the were SoC well verified, and the goal becomes verification of connection coverage among the IPs, and subsystems and the SoCs performance coverage of behaviors in comparison with the specification. At TESDA, we focus the development of our technology on SoC level connections and performance coverage.  

Learn More About AutoDV Benefit:

Are you ready for your SoC verification to the next level?

AutoDV is your go-to for faster, more consistent, and more successful projects.

  • Comprehensive Reuse Framework: The TESDA verifier library is a centralized knowledge base that helps us seamlessly reuse across teams and projects.
  • Aligned Methodologies: Align user methodologies with corporate processes in order to have smooth, consistent results. Automatically parse SoC and attach to verifier for test benches that can be generated in record time for each new revision across teams and projects.
  • Automatic Test Bench Generation: Leverage automatic SoC parsing and verifier attachment to generate test benches for each new revision in record time.
  • User-Friendly Design: The framework is inspired by simplicity so that newcomers can use it easily, allowing you to focus on innovation while not losing sight of technical details.