At IP/block level, the main concern is functional coverage of individual IPs. While at SoC level, we assume all IP/blocks and subsystems within the SoC were well verified, and the goal becomes verification of functional coverage after integration of the IPs and subsystems and the performance coverage of behaviors of the SoC in comparison with the specification. TESDA focuses our technology development on the SoC level functional and performance coverage.
AutoDV is an ideal solution for SoC-level verification. By encapsulating and reusing past experiences, it significantly enhances the efficiency of verification. With AutoDV, you can encapsulate verification expertise at the SoC level and utilize the Transactor library as a framework for reuse by all users, thereby accelerating the verification process.
Built for electronic system design optimization
Revolutionary Technology
TESDA Explorer Suite® will fully leverage the traffic information gathered by Intelligent Scout® to optimize the system design by
–Knowledge abstraction
–Symptom identification
–Solution prescription
Engineering Services
Growth with Partners
TESDA not only provides complete education and training services for our employees, but also will provide this high-quality service to our external partners in the near future. This service will also fully integrate with our tools to provide the most efficient and valuable solutions to our partners.
最新消息
We’re thrilled to be a Gold Sponsor at DVConTaiwan2023! Join us on Sep 7, 2023, at NYCU, Hsinchu, Taiwan. Experience our upcoming SoC verification tool, AutoDV, and grab the chance to win a personal version on its official release!
Our CEO has also been invited to join the Steering Committee, engage with our talented team, and grab some exclusive giveaways. Let’s shape the future of tech together!
For more info, please visit: www.dvcontaiwan.org. We can’t wait to see you there!
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Providing dedicated and professional DV services for leading semiconductor manufacturers
